[23.05.2026] Our lab members Enes Abdulhalik, Mehmet Emin Baytekin, Gizem Sungu Terci, Alp Arslan Bayrakci, and Alihan Turan have published their latest research paper, "A Modular Graph Coloring Abstraction for Register Allocation in LLVM: Design and Evaluation," in the Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (ICHORA 2026).

Abstract Summary: Register allocation is a critical, NP-hard optimization phase in modern compiler design that directly impacts program execution performance. Integrating new, specialized allocation strategies into complex frameworks like LLVM often requires intrusive and monolithic modifications. This study introduces a novel, "Modular Graph Coloring Abstraction" that decouples allocation algorithms from LLVM’s core infrastructure. This design enables developers to implement and test unique register allocation heuristics without modifying the compiler's primary codebase.

Why It Matters: The proposed abstraction layer significantly enhances both compilation flexibility and architectural portability. Experimental evaluations presented at ICHORA 2026 demonstrate that this modular design maintains high code quality while effectively managing the inherent complexity of modern compiler backends. This framework provides a scalable and robust solution for researchers looking to optimize register management for emerging RISC-V based architectures and custom high-performance SoCs.

[23.05.2026] Our lab members Muhammet Emin Akgün and Alp Arslan Bayrakci have published their latest research paper, "A Lightweight Hardware Accelerator for Fixed-Point Least-Squares Estimation in RISC-V SoCs," in the Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (ICHORA 2026).

Abstract Summary: Least-Squares Estimation (LSE) is a fundamental mathematical technique widely used in signal processing, system identification, and adaptive control. However, executing LSE algorithms on resource-constrained edge devices frequently induces high computational latencies and heavy CPU overhead. This study introduces a lightweight hardware accelerator tailored for fixed-point LSE computations within RISC-V System-on-Chips (SoCs). By optimizing the matrix manipulation pipelines and leveraging specialized fixed-point arithmetic units, the proposed accelerator unloads intensive matrix operations from the main scalar RISC-V core without incurring significant area or power penalties.

Why It Matters: Deploying real-time estimation algorithms on edge processors typically requires expensive floating-point hardware or compromises on processing speed. This research bridges that gap by providing a highly cost-efficient, low-power fixed-point hardware co-processor. Presented at ICHORA 2026, the experimental evaluations demonstrate substantial throughput enhancements and accelerated convergence rates compared to pure software-defined execution, offering a scalable and robust solution for real-time, embedded signal processing and next-generation IoT edge workloads.

[01.11.2024] Enes Abdulhalik, has been nominated as teaching and research assistant in Computer Engineering Department of Gebze Technical University. He will be conducting research on FPGA based acceleration of graph coloring algorithms.

Congratulations!! We look forward to seeing you among our assistants! May your journey as a research assistant be filled with discoveries and achievements!

[02.10.2024] A PhD is typically a challenging journey, but Gizem's path was filled with extraordinary difficulties. Despite the obstacles, she persevered and successfully completed her degree. Congratulations to Gizem Süngü Terci for earning her PhD in Computer Engineering today! Her PhD Thesis is about a new generation of evolutionary algorithms utilizing Bitvertex represenation to accelerate graph coloring for register allocation.

[30.09.2024] The paper titled as Hybrid Cost-Effective Decapsulation of Chips for Successful Laser Fault Injection and authored by Furkan Bekar and Alp Arslan Bayrakci has been accepted by the 17th International Conference on Information Security and Cryptology.

The abstract is as follows: As attacking techniques evolve, hardware security has become increasingly critical. This paper presents a hybrid decapsulation technique combining mechanical and chemical etching to prepare chips for laser fault injection (LFI). We propose a two-stage process: initial mechanical etching using a milling machine to precisely thin the chip down to a 100 micron layer above the die surface, followed by repetitive chemical etching with fuming nitric acid to expose the die while protecting wire bonds. The method is validated through functional tests and an actual LFI attack targeting the AES encryption algorithm on ATmega328P chips. The functional test confirms the accurate operation of the chip after the decapsulation, while the executed LFI attacks successfully modify the ciphertext output, demonstrating the effectiveness of the hybrid decapsulation in transforming chips into suitable candidates for LFI attacks.

[29.09.2024] The paper titled as Parallelization of BitColor Algorithm via Multithreading and GPU for Graph Coloring and authored by Burak Kocausta, Gizem Sungu Terci and Alp Arslan Bayrakci has been accepted by the 9th International Conference on Computer Science and Engineering (UBMK 2024). Especially congratulations for Burak as he has managed that success during his ungraduate study.

The abstract is as follows: The graph coloring problem is a fundamental NPhard problem with numerous applications in scheduling, register allocation, and network optimization. Traditional sequential algorithms for graph coloring are computationally expensive, particularly for large-scale graphs. In this paper, we propose the Parallel BitColor Algorithm (PBitCo), an extension of the BitColor framework, designed to exploit the parallel processing capabilities of modern CPU and GPU architectures. The PBitCo algorithm utilizes bitwise operations to reduce time complexity and employs parallel execution on widely accessible platforms to further enhance performance. We implemented and tested the algorithm on various graph instances, comparing its performance against conventional graph coloring methods. Our results demonstrate that PBitCo achieves significant speedups, with the GPU implementation delivering up to 10x improvement over baseline methods.

[20.09.2024] Enes Abdulhalik, previously an undergraduate member of GTU ICL, has started his new journey as an MSc student member of the lab. Even before graduating he co-authored a journal paper with Gizem and Alp. Wishing you all the best in this new chapter of your career, Enes.

He will be studying on register allocation problem and search its optimal solution space utilizing both GPU and FPGAs.

[26.09.2024] After a long journey starting with an MSc in GTU ICL Lab, finally Fatma Nur Esirci has successfully completed her PhD degree. She is the first PhD graduate of this lab. Congratulations to Fatma Nur Esirci for earning her PhD in Computer Engineering today! Her PhD Thesis is titled as SUPPRESSING VARIATIONS BY SPATIAL CORRELATIONS TO AVAIL DELAY-BASED HARDWARE TROJAN DETECTION.

[20.08.2024] Our lab members Gizem Süngü Terci, Enes Abdülhalik, Alp Arslan Bayrakcı, and Betül Boz have published their latest paper, "BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation," in IEEE Access (Volume 12).

Abstract Summary: Register allocation is vital for optimizing program execution times, yet its complexity often leads to computational bottlenecks on modern CPU architectures. This study presents BitEA, a novel evolutionary optimization algorithm rooted in bitwise operations. By introducing a unique "BitVertex" graph representation, the algorithm parallelizes crucial evolutionary processes using native bitwise logic.

Why It Matters: BitEA achieves an unprecedented speedup—outperforming existing methods by up to 60 times on DIMACS benchmarks—while simultaneously delivering higher solution quality (lower chromatic numbers). This contribution significantly advances the scalability and feasibility of using evolutionary heuristics in modern compiler design.